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APLUS
MAKE YOUR PRODUCTION A-PLUS
ASM2012CB DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Sales E-mail: Mr. Jason sales@aplusinc.com.tw Technology E-mail: Mr. George service@aplusinc.com.tw
Address: 3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei, Taiwan 115, R.O.C. (115) 32 3 10. TEL: 886-2-2782-9266 FAX: 886-2-2782-9255 WEBSITE : http: //www.aplusinc.com.tw
ASM2012CB ASM2012CB - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR
1.0 General Description The AM4DD0207 is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5V Internal Program ROM: 4K x 10-bit 1 sets of 16-bit DPR can access up to 64K x 10 bits data memory space Data Registers: * 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 4-bit Output Port B (2Dh) * PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 The Voice function can be implemented by microprocessor instruction * One 8-bit COUT output for ASM2012CB
1
Rev 1.0
2002/07/12
ASM2012CB
FIGURE 1.1 : Block Diagram of ASM2012CB
Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[15:12]) =0000b ADDR[15:0] Stack(12) (2-Level) 0 ROM_ADDR[15:0] 1 DPR3,2,1 DPR[15:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder
PCLATCH(8) PCH(8)
DLATCH(10) ROM_Data[9:0]
Data Bus[3:0] Accumlator(4)
Instruction Bus [9:0]
SRAM
ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh
Timer0(9)
PRA(4) PRB(4) PRC(4)
P1,P2,P3,P4 enter test mode
( Voice synthesizer )
Clock Generator Test select Power on Reset RESET pin PRA0
weak or strong pull-low for PRA, PRB, PRC OSC VDD/GND PRASL(4)
One-Channel
Reset Chip Reset Chip
COUT
COUT
2
Rev 1.0
Instruction Bus [9:0]
Control Signal
2002/07/12
ASM2012CB
FIGURE 1.2 : External ROM Map of ASM2012CB
PC[11:0]
12bit x 2 STACK 16-bit Data Pointer Reset Vector
00000h
00080h
Reserved for Testing
Program and data ROM
00080h-003FFh 00400h 00000h-00FFFh
00000h-0FFFFh
00FFFh(4K)
Data ROM
0FFFFh(64Kx10-bits)
3
Rev 1.0
2002/07/12
ASM2012CB
1.2 Pin-Out ASM2012CB Pin-Out
PRC1 PRC0/RESET I I STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Input port with programmable strong pull-low or weak pull-low or fixinput-floating capability Input port with programmable strong pull-low or weak pull-low or fixinput-floating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fixinput-floating capability
PRA3-1 PRA0/RESET
I/O I/O
OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3
I I O I I O I O I
Std./O.D. STI Std./O.D.
1.3 Application circuit
4
Rev 1.0
2002/07/12
ASM2012CB
1.4 Bonding Diagram
19 RC3
18 RC2
17 RC1
16 RC0
15 GND2
14 VDD2
13 TEST
12 OSC
( 64K x 10-bit ) Block ROM
Y=1780+80 (um)
RA3 RA2 RA1 RA0 VDD1
ASM2012CB
COUT GND1 RB0 RB1 RB2 RB3
1
2
3
4
5
6
7
8
9
10
11
X= 1540+80 (um)
Substrate must be connected to GND.
ASM2012CB Pad Location PAD # PAD Name X 1 RA3 -682.16 2 RA2 -559.84 3 RA1 -437.52 4 RA0 -315.2 5 VDD1 -191.28 6 COUT 71.12 7 GND1 189.52 8 RB0 307.92 9 RB1 430.24 10 RB2 552.56 Chip Size: X= 1540+80 (um), Y=1780+80 (um) Y PAD # PAD Name X Y -772.68 11 RB3 674.88 -772.68 -772.68 12 OSC 633.56 804 -772.68 13 TEST 432.48 804 -772.68 14 VDD2 273.16 804 -772.68 15 GND2 134.68 804 -772.68 16 RC0 -51.76 804 -772.68 17 RC1 -248.4 804 -772.68 18 RC2 -454.24 804 -772.68 19 RC3 -650.88 804 -772.68
5
Rev 1.0
2002/07/12
ASM2012CB
1.5 DC Characteristics for ASM2012CB
SYMBOL VDD Isb Iop Iih Ioh Iol Cout dF/F dF/F PARAMETER OPERATING VOLTAGE SUPPLY CURRENT STANDBY OPERATING VDD 3 5 3 5 3 5 5 3 5 3 5 3 5 -10 -20 MIN. 2.4 TYP. 3 MAX. 5.5 1 1 UNIT V uA mA uA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low)
INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT DA CURRENT OUT (FULL SCALE) FREQUENCY STABILITY Fosc VARIATION
2 7 3 9 -5.2 -3 -8 7 20 4 5.2 10 20
mA
4MHz, RM (IO ports)
% %
Fosc(3v- 2.4v) Fosc (3v) VDD=3V, Rosc=200k, 4MHz
FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 300 2.56 200 3.92
R osc & Freq. 8 Freq. MHz 6 4 2 0 0 100 200 R osc k ohm 300 400
130 5.48
110 7.11
7.11 5.48 3.92 2.56
6
Rev 1.0
2002/07/12

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